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Are you an DoD Cleared FPGA/ASIC Design Engineer looking to join one of the top Aerospace and Defense industries?

Are you looking to further your career and grow?

Do you have experience with a proven track record of implementing complex algorithms targeting ASIC/FPGAs?

If you answered yes to those three questions, then apply today!

Acara Solutions seeks highly qualified candidates to work on-site with our client in Camden, NJ. Interested?

Here's what you'd do:

• The FPGA/ASIC Design Engineer will be responsible for the architecture, implementation, verification/validation through Software integration tests for delivery of complex FPGAs AND/OR ASICs systems.
• This is a key, high-impact, high-visibility role in the organization to ensure robust quality and delivery of Communication products for National Security.
• Develop architectures for implementing high-throughput complex designs involving Cryptographic Algorithms (VHDL) with high-speed protocols-NVMe, PCIe/SRIOV, 10G-400G Ethernet, TCP/IP, and IP development/integration targeting ARM SOC FPGAs (Xilinx MPSOC) OR ASICs.
• Responsible for writing/debugging tests/sequences for End-to-End simulation on the UVM framework, with System Verilog Assertions, and writing/debugging C++-based SW-driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux.
• The client has deployed state-of-the-art EDA flows/methodologies, including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA, including HLS, Mentor Questa family, VIPs for UVM, Clock Domain Crossing (CDC), and Catapult (HLS).

Here's what you'll get:

Pay: $125/hr.

Hours: Daily hours 9/80.

Length: Temp to Direct (6 Months).

Sounds like a good fit?

APPLY TODAY

About Acara Solutions

Acara is a premier recruiting and workforce solutions provider-we help companies compete for talent. With a legacy of experience in various industries worldwide, we partner with clients, listen to their needs, and customize visionary talent solutions that drive desired business outcomes. We leverage decades of experience to deliver contingent staffing, direct placement, executive search, and workforce services worldwide.

• Active Secret DoD Clearance.
• Bachelor's Degree in Electrical Engineering or Computer Science.
• Minimum of 3 years experience with a proven track record of implementing complex algorithms targeting ASIC/FPGAs.
• Minimum of 3 years experience in VHDL and FPGA design/debugging - Xilinx FPGA / Vivado.

• Master's Degree in Electrical Engineering or Computer Science.
• Excellent Analytical/debugging skills.
• Good verbal, written, and presentation skills.
• High-Level Synthesis (HLS) with Vivado.
• Embedded SW C++ (OOP) and System Verilog Assertions (SVA).
• Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet).

Additional Information:

• Upon offer of employment, the individual will be subject to a background check and a drug screen.
• In compliance with federal law, all persons hired will be needed to verify identity and eligibility to work in the United States and to complete the necessary employment eligibility verification form upon hire.
• Under the International Traffic in Arms Regulations (ITAR), all employees assigned to this client must provide documentation verifying their status as a 'U.S. Person,' as defined in ITAR clause 120.15. A U.S. Person is a protected individual under the anti-discrimination provisions of U.S. immigration laws.