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Job#: 2043664

Job Description:

Software Design Test Engineer 3

Typical Day in the Role * Purpose of the Team: The SPARC team is responsible for next Gen server class hardware and that that resides in Azure. * Key projects: This role will contribute to working on the next Gen hardware. * Typical task breakdown and operating rhythm: The role will consist of writing test case for validation, conducting finding meetings, and collaborating with team members. Compelling Story & Candidate Value Proposition * What makes this role interesting? - This role provides the opportunity to work on unique tasks and will get exposer to entire industry Candidate Requirements * Years of Experience Required: 5-7 overall years of experience in the field. * Degrees or certifications required: bachelors degree in computer science and electoral engineering degree is required to be eligible for this role. * Disqualifiers: Candidates with no experience with UVM or SystemVerilog will not be eligible for the role. * Best vs. Average: The ideal resume would contain pre silicon validation experience (DV), and the ability to a test bench development or test writing in UVM. A bill plus would be knowing C. * Performance Indicators: Performance will be assessed based on quality of work and peer reviews. Top 3 Hard Skills Required + Years of Experience 1. Minimum 5-7 years experience with UVM and System Verilog at both block level and chip level. 2. Minimum 5-7 years experience with RTO 3. Minimum 5-7 years experience with developing portable C-based firmware Hard Skills Assessments * Expected Dates that Hard Skills Assessments will be scheduled: ASAP * Hard Skills Assessment Process: The assessment process will include 2 rounds 30 minutes each * Required Candidate Preparation: Candidates should have _NA_ prepared prior to the assessment. Summary: The main function of a Software Design Engineer is to develop, implement, and document all testing activities, including test planning, test documentation, test execution, defect tracking and reporting, including follow-up and issue resolution. Requirements: 1. Proficiency in building testbenches and conducting tests using Universal Verification Methodology (UVM) and SystemVerilog at both block level and chip level. 2. Experience in developing portable C-based firmware tests specifically tailored for RISC-V microprocessors. 3. Ability to create comprehensive test plans and write tests to ensure complete feature coverage. The requirements for a contractor capable of building UVM Testbenches, working on C-based tests for RISC-V, and focusing on design verification would include, but not be limited to: Proficiency in building testbenches and conducting tests using Universal Verification Methodology (UVM) and SystemVerilog at both block level and chip level. Experience in developing portable C-based firmware tests specifically tailored for RISC-V microprocessors. Ability to create comprehensive test plans and write tests to ensure complete feature coverage. Expertise in writing constraints, assertions, and achieving functional coverage. Skills in writing Makefiles and scripts to support a verification infrastructure. Familiarity with Agile development methodologies, including participation in code reviews, sprint planning, and frequent deployment. Capability to develop and maintain nightly regression testing Azure DevOps & Github pipelines. Experience or willingness to handle a DevOps infrastructure These requirements would ensure that the contractor has the necessary skills and experience to perform design verification tasks effectively and contribute to the development and maintenance of the verification infrastructure. Qualifications: BS and/or MS in Electrical Engineering or equivalent degree 8+ years of RTL design, UVM Ve