Job Information
Intel Verification Engineer Lead in San Jose, California
Job Description
In Q4 2023, Intel® announced Altera® will be reported as a separate business unit beginning on January 1, 2024, with ongoing support from Intel®. This position is associated to that standalone business strategy and is expected to fully transition to a standalone company at some time in the future.
Come and join us...Intel® is seeking highly qualified candidates to join our Altera® - Platform Solutions Group (PSG) as a Pre-Silicon Verification Engineer Lead.
As a Pre-Silicon Verification Engineer Lead, you will be responsible for Testbench architecture, verification strategy, creating detail test plan, driving and execution of verification flow and implementations at block level, sub system, multi sub system and full chip level. You will be expected to be actively engaged, use tools, participate in high-level silicon specifications, work closely with SoC architects and digital block leads to provide the best input for verification scope and effort toward the success of silicon tape-out/tape-in with world-class commercial quality.
Your responsibilities as Pre-Si Senior Verification Engineer Lead will include, but not limited to:
Work closely with cross functional teams in understanding the chip architecture and planning the verification tasks for the entire DV team.
Work on Verification activities to deliver Microcontroller-based IP (Hardware and Firmware).
Own and drive execution strategy and execution on Design Verification domains.
Architect Test bench Infrastructure (monitors, scoreboards/checkers, BFMs, etc.) and Verification methodologies (test content, sequences, etc.) to enable execution.
Collaborate with design and architecture teams to ensure alignment on feature scoping, staging, and verification coverage.
Development and integration of verification environment components utilizing UVM/System Verilog.
Creating Verification/Test plans from Functional Specifications.
Development, simulation, and debug of UVM and C based test cases.
Experience in Functional coverage, code coverage and System Verilog assertions.
Drive initiatives for continuous improvement of IP / SOC quality.
Mentor engineers and provide technical guidance to the team.
Qualifications
You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Education
- Bachelor's degree in electrical engineering, Computer Engineering, Computer Science, or related field.
Minimum Qualifications
10+ years of total experience, experience should include:
Verifying ASICs in Full Chip or SoC area.
Microcontroller based IP Verification.
Ethernet protocol experience.
System Verilog and OVM/UVM.
Scripting languages (e.g. Perl, Python, TCL, Shell, etc.).
Preferred Qualifications
3rd party verification IPs.
Verification experience on Serdes, PCIe, USB.
Experience with debugging.
Experience working with various chip design disciplines and cross site teams.
Verification of the microarchitecture using industry standard Formal Verification tools and technologies based on latest model checking and equivalence checking algorithms on world class design IPs.
Experience on Verification of FPGA Based architecture designs.
Inside this Business Group
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.
Other Locations
US, OR, Hillsboro; US, TX, Austin
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)
Annual Salary Range for jobs which could be performed in US, California: $162,041.00-$259,425.00
*Salary range dependent on a number of factors including location and experience
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.